A random-access memory (RAM) is an array of memory cells organized in rows and columns. Each memory cell can contain a value of 0 or 1 and is given an address which is usually a concatenation of its row number and column number expressed in binary notation. In order to read or write the contents of a memory cell, its row and column number is applied to the corresponding address decoders which will activate the appropriate row (or word) lines and bit lines. A word line is a wire that allows the connection of a row of memory cells to the bit lines through access transistors. The bit lines carry the actual data values from/to the memory cells to/from the data output/input of the memory. A multi-port memory has several sets of work lines and bit lines that can be addressed independently.
Multi-port memories are very susceptible to two kinds of shorts. Two specific failures are shorts between adjacent work lines from different ports and shorts between bit lines located in the same (or adjacent) column of memory cells but originating from different ports.
Simultaneous read and/or write operations on the various ports can cause errors under specific circumstances. For example, a memory cell could be read correctly from one port only but could fail to return the correct value if accessed from 2 ports at the same time.
A port is said to be selected if it can perform read or write operations during a test.
A port is said to be active if it is used to apply the single-port test algorithm. In the case of Read-write ports, it is possible that only half, ie the Read or the Write portion of this port, is active.